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| www..com (R) EP312 & EP324 Classic EPLDs Data Sheet April 1995, ver. 1 Features s s s s s s s s s s s s s s High-performance EPLDs with 12 macrocells (EP312) or 24 macrocells (EP324) - Combinatorial speeds as fast as 25 ns - Counter frequencies of up to 33.3 MHz - Pipelined data rates of up to 66 MHz Multiple 20-pin PAL and GAL replacement and integration Device erasure and reprogramming with advanced, nonvolatile EPROM configuration elements Programmable registers providing D, T, JK, and SR flipflops with individual Clear and Clock controls Dual feedback on all macrocells for implementing buried registers with bidirectional I/O Programmable-AND/allocatable-OR structure allowing up to 16 product terms per macrocell DataShee Two product terms on all macrocell control signals Programmable inputs (8 in EP312, 10 in EP324) configurable as .com latches, registers, or flow-through input Available in windowed ceramic and one-time-programmable (OTP) plastic packages with 24 to 44 pins: - 24-pin ceramic and plastic dual in-line package (CerDIP and PDIP) - 28-pin plastic J-lead chip carrier (PLCC) - 40-pin CerDIP and PDIP - 44-pin PLCC One global Clock pin; one global Input Latch Enable/Input Clock/Input (ILE/ICLK/INPUT) pin Programmable "standby" option for low-power operation Programmable Security Bit for total protection of proprietary designs 100% generically testable to provide 100% programming yield Software design support with the Altera PLDshell Plus software and a wide range of third-party tools; programming support through third-party vendors General Description The CMOS EPROM EP312 and EP324 devices have a versatile macrocell structure and I/O architecture, which allow them to implement highperformance logic functions effectively. The EP312 and EP324 input and macrocell features are a superset of features offered by PAL/GAL devices. Therefore, EP312 and EP324 devices can be used as an alternative to multiple PAL/GAL devices, SSI and MSI logic devices, or low-end gate arrays. 1 .com Altera Corporation A-DS-312/324.01 DataSheet 4 U .com www..com EP312 & EP324 Classic EPLDs EP312 and EP324 devices operate in high-performance systems with low power consumption. The programmable standby function provides "zero" power consumption for applications where performance can be traded for power savings. Functional Description The EP312 and EP324 architecture is based on a sum-of-products programmable-AND/allocatable-OR structure. EP312 and EP324 devices can implement combinatorial and sequential logic functions, as well as combinatorial-register and register-combinatorial-register logic forms, to easily accommodate state machine designs. Figure 1 and Figure 2 show block diagrams of the EP312 and EP324 architectures. The EP312 device contains 12 I/O macrocells and 8 programmable input structures; the EP324 device contains 24 I/O macrocells and 10 programmable input structures. EP312 and EP324 macrocells are divided into 2 rings for product-term allocation. Both devices have 2 additional inputs that can be programmed either as combinatorial inputs or Clock inputs. Each input structure can be individually configured as a latch, register, or flow-through input. Input latches and registers can be clocked synchronously or asynchronously. t4U.com Figure 1. EP312 Block Diagram Clock/Input 1 DataShee .com Global Clock Input/Register/Latch Macrocell 1 Macrocell 2 Macrocell 3 Macrocell 4 Macrocell 5 Macrocell 6 1 2 3 4 5 6 Input 1 Input 2 Input 3 Input 4 Input 5 Input 6 Input 7 Input 8 Ring 1 Global Bus Global Clock Macrocell 7 Macrocell 8 Macrocell 9 Macrocell 10 Macrocell 11 Macrocell 12 7 8 9 10 11 12 Ring 2 Input Latch Enable/Input Clock/Input 2 .com 2 Altera Corporation DataSheet 4 U .com www..com EP312 & EP324 Classic EPLDs Figure 2. EP324 Block Diagram Input/Register/Latch Clock/Input 1 Global Clock Input 1 Input 2 Input 3 Input 4 Input 5 Input 6 Input 7 Input 8 Global Bus Macrocell 1 Macrocell 2 Macrocell 3 Macrocell 4 Macrocell 5 Macrocell 6 Macrocell 7 Macrocell 8 Macrocell 9 Macrocell 10 Macrocell 11 Macrocell 12 Global Clock Macrocell 13 Macrocell 14 Macrocell 15 Macrocell 16 Macrocell 17 Macrocell 18 Macrocell 19 Macrocell 20 Macrocell 21 Macrocell 22 Macrocell 23 Macrocell 24 1 2 3 4 5 6 7 8 9 10 11 12 Ring 1 t4U.com Input 9 Input 10 .com 13 14 15 16 17 18 19 20 21 22 23 24 Ring 2 DataShee Input Latch Enable/Input Clock/Input 2 The EP312 and EP324 architectures include the following features: s s s s Macrocells Product-term allocation Programmable inputs Power-on characteristics Macrocells Each EP312 and EP324 macrocell contains 16 product terms (see Figure 3). Half of the product terms are available to support logic functions; half are dedicated to the macrocell control signals. The inputs to the AND array originate from the true and complement signals of the programmable input structure, the dedicated inputs, and the 2 feedback paths from each I/O macrocell to the global bus. .com Altera Corporation 3 DataSheet 4 U .com www..com EP312 & EP324 Classic EPLDs Figure 3. EP312 & EP324 Macrocell Logic Array Lower Half Product Terms 1 to 4 to Previous Macrocell from Previous Macrocell Global Clock Output Enable Output Multiplexer 4 Allocation Control 4 Upper Half Product Terms 1 to 4 Invert Control PRN D/T Q CLR t4U.com ILE/ICLK Programmable Register DataShee .com Clock Multiplexer to Next Macrocell from Next Macrocell The eight product terms available for implementing logic functions are divided into two equal groups, and can be used in other macrocells. Each macrocell provides a dual feedback to the logic array. The eight product terms for control functions support the following four control signals, with two product terms each: Output Enable (OE), Preset, Clear, and asynchronous Clock. When the global Clock (CLK) signal synchronously clocks a macrocell register, it cannot function as an input to the logic array. However, the global Clock can simultaneously function as an input to the logic array and as an asynchronous, non-global Clock. .com 4 Altera Corporation DataSheet 4 U .com www..com EP312 & EP324 Classic EPLDs To implement registered functions, each macrocell register can be individually programmed for D, T, JK, or SR operation. If necessary, the register can be bypassed for combinatorial operation. The XOR gate can implement active-high or active-low logic, or use DeMorgan's inversion to reduce the number of product terms required to implement a function. Registers are cleared automatically during power-up. The macrocell output can be fed back to the logic array via two paths. Pin feedback that is connected after the output buffer can be used to implement bidirectional I/O; if internal feedback is used for a buried register or logic function, the pin feedback can be used as an input. Product-Term Allocation t4U.com In EP312 and EP324 devices, product-term resources can be taken from one macrocell and used in another. For product-term allocation, macrocells in both the EP312 and EP324 are divided into 2 rings. The EP312 has 6 macrocells per ring; the EP324 has 12 macrocells per ring. Product terms from one macrocell can be allocated to adjacent macrocells in the same ring. Product terms are allocated in groups of 4, and a macrocell can borrow up to 8 product terms (4 from each adjacent DataShee macrocell). .com Table 1 and Table 2 show the product-term allocation rings for the EP312 and EP324 devices, respectively. The Altera PLDshell Plus design software automatically allocates product terms. .com Altera Corporation 5 DataSheet 4 U .com www..com EP312 & EP324 Classic EPLDs Table 1. EP312 Product-Term Allocation Rings Ring 1 Current Macrocell 1 2 3 4 5 6 Ring 2 Previous Macrocell 6 1 2 3 4 5 Next Macrocell 2 3 4 5 6 1 Current Macrocell 7 8 9 10 11 12 Next Macrocell 8 9 10 11 12 7 Previous Macrocell 12 7 8 9 10 11 Table 2. EP324 Product-Term Allocation Rings Ring 1 Current Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 Ring 2 Previous Macrocell 2 3 5 6 12 1 7 8 9 10 11 Sheet4U.com Next Macrocell 7 1 3 4 5 8 9 10 11 12 6 Current Macrocell 13 14 16 17 18 19 20 21 22 23 24 Next Macrocell 19 13 14 15 16 17 20 21 22 23 24 18 Previous Macrocell 14 15 16 17 18 24 13 19 20 21 22 23 Data D a 2t a S h e4 e t 4 U 15 c o m . Programmable Inputs Figure 4 shows a block diagram of the EP312 and EP324 input structure. The user-programmable inputs can be individually configured to operate in the following modes: s s s s s .com 6 Input D register, synchronously clocked Input D register, asynchronously clocked Input D latch, synchronously clocked Input D latch, asynchronously clocked Flow-through input Altera Corporation D a t a S 4 Ue c o m h .et www..com EP312 & EP324 Classic EPLDs Figure 4. EP312 & EP324 Input Structure Product Term from Logic Array INPUT D Q to Logic Array ILE/ICLK/INPUT Synchronous/ Asynchronous Select Latch/Register Select t4U.com The ILE/ICLK/INPUT pin is a dedicated input to the logic array. For synchronous operation, the ILE/ICLK/INPUT pin becomes a global ILE/ICLK input to all latch/register/input structures; for asynchronous operation, a separate product term in the logic array is used to derive the ILE/ICLK signal for each input structure. Because the Clock signal for each programmable input can be selected individually, a combination of asynchronously and synchronously clocked inputs is available. Flowthrough operation occurs when the ILE product term is tied to VCC. Data is latched or clocked on the falling edge of ILE/ICLK in synchronous mode. DataShee .com Power-On Characteristics EP312 and EP324 inputs and outputs respond between 6 s and 10 s after power-up, or after a power-loss/power-up sequence. All macrocells programmed as registers are set to a logic low on power-up. Input registers are not reset on power-up and their values are indeterminate. Input latches reflect the state of the input pins on power-up. Design Security EP312 and EP324 devices contain a programmable Security Bit that controls access to the data programmed into the device. When this bit is programmed, a proprietary design implemented in the device cannot be copied or retrieved. This feature provides a high level of design security, since programmed data within EPROM configuration elements is invisible. The Security Bit that controls this function, as well as all other program data, is reset when a device is erased. EP312 and EP324 devices contain a programmable Turbo Bit that controls the automatic power-down feature, which enables the low-standbypower mode (I CC1). When the Turbo Bit is turned on, the low-standbypower mode is disabled. All AC parameters are tested with the Turbo Bit turned on. When the device is operating with the Turbo Bit turned off (non-turbo mode), a non-turbo adder must be added to the appropriate AC parameter to determine worst-case timing. The non-turbo adder is specified in the "AC Operating Conditions" tables in this data sheet. Turbo Bit .com Altera Corporation 7 DataSheet 4 U .com www..com EP312 & EP324 Classic EPLDs Generic Testing EP312 and EP324 devices are fully functionally tested and guaranteed. Complete testing of each programmable EPROM configuration element and all internal logic elements ensures 100% programming yield. AC test measurements are taken under conditions equivalent to those shown in Figure 5. Figure 5. EP312 & EP324 AC Test Circuits Power-supply transients can affect AC measurements. Simultaneous transitions of multiple outputs should be avoided for 460 accurate measurement. Threshold tests Device must not be performed under AC conditions. Large-amplitude, fast ground- Output current transients normally occur as the device outputs discharge the load capacitances. When these transients flow 238 through the parasitic inductance between the device ground pin and the test-system ground, significant reductions in observable noise immunity can result. VCC To Test System C1 (includes JIG capacitance) t4U.com DataShee Test programs are used and then erased during the early stages of a device production flow. EPROM-based devices in one-time-programmable .com packages also contain on-board logic test circuitry to allow verification of function and AC specifications during production flow. Software & Programming Support f The EP312 and EP324 are supported by the Altera PLDshell Plus design software and other industry-standard logic compilers (e.g., ABEL, CUPL, PLDesigner, LOG/IC, and iPLS II). The EP312 and EP324 are supported by third-party programming hardware. For more information on software support with PLDshell Plus, go to the PLDshell Plus/PLDasm User's Guide, which is available from the Altera Literature Department; refer to the Programming Hardware Manufacturers Data Sheet in the Altera Data Book for more information on third-party programming hardware support. .com 8 Altera Corporation DataSheet 4 U .com www..com EP312 & EP324 Classic EPLDs Figure 6 shows the typical supply current (ICC) versus frequency for EP312 and EP324 devices. Figure 6. EP312 & EP324 ICC vs. Frequency EP312 EPLDs 120 EP324 EPLDs 240 100 200 ICC Active (mA) Typ. ICC Active (mA) Typ. Turbo 80 Turbo 160 60 VCC = 5.0 V TA = 25 C 120 VCC = 5.0 V TA = 25 C 40 Non-Turbo 80 Non-Turbo 20 40 t4U.com 10 20 30 40 10 20 30 40 DataShee Frequency (MHz) Frequency (MHz) .com .com Altera Corporation 9 DataSheet 4 U .com www..com EP312 & EP324 Classic EPLDs Figure 7 shows the maximum output drive characteristics of EP312 and EP324 I/O pins. Figure 7. EP312 & EP324 Output Drive Characteristics EP312 & EP324 EPLDs 50 Output Current (mA) Typ. 40 IOL 30 20 VCC = 5.0 V TA = 25 C IOH 10 IO 1 2 3 4 5 VO Output Voltage (V) t4U.com DataShee .com .com 10 Altera Corporation DataSheet 4 U .com www..com EP312 & EP324 Classic EPLDs Absolute Maximum Ratings Symbol VCC VI TSTG TAMB Supply voltage DC input voltage Storage temperature Ambient temperature Note (1) Conditions Note (2) Notes (2), (3) Note (4) Parameter Min -2.0 -0.5 -65 -10 Max 7.0 VCC + 0.5 150 85 Unit V V C C Recommended Operating Conditions Symbol VCC VIN VO TA TA tR tF Supply voltage Input voltage Output voltage Operating temperature Operating temperature Input rise time Input fall time For commercial use For industrial use Parameter Conditions Min 4.75 0 0 0 -40 Max 5.25 VCC VCC 70 85 500 500 Unit V V V C C ns ns DC t4U.com Operating Conditions Symbol VIH VIL VOH VOH VOL II IOZ ISC Note (5) Parameter DataShee High-level input voltage Low-level input voltage High-level TTL output voltage High-level CMOS output voltage Low-level output voltage Input leakage current Tri-state output leakage current Output short-circuit current .com Note (2) Note (2) Conditions Min 2.0 -0.3 2.4 3.84 Max VCC + 0.3 0.8 Unit V V V V IOH = -4.0 mA DC, VCC = min. IOH = -2 mA DC, VCC = min. IOL = 8 mA DC, VCC = min. VCC = max., GND < VIN < VCC VCC = max., GND < VOUT < VCC VCC = max., VOUT = 0.5 V, Note (6) 0.45 10 10 -30 -90 V A A mA Capacitance Symbol CIN COUT CCLK CCLK CVPP Note (5) Parameter Conditions VIN = 0 V, f = 1.0 MHz VOUT = 0 V, f = 1.0 MHz VOUT = 0 V, f = 1.0 MHz VOUT = 0 V, f = 1.0 MHz Min Max 8 15 12 15 25 Unit pF pF pF pF pF Input capacitance I/O capacitance EP312 ILE/ICLK/INPUT pin capacitance EP324 ILE/ICLK/INPUT pin capacitance VPP pin capacitance Note (7), f = 1.0 MHz .com Altera Corporation 11 DataSheet 4 U .com www..com EP312 & EP324 Classic EPLDs ICC Supply Current Note (5) EP312 EP324 Symbol ICC1 ICC3 Parameter Standby current VCC supply current Conditions VCC = max., VIN = VCC or GND, standby mode, Note (8), (9) VCC = max., VIN = VCC or GND, no load, fIN = 1 MHz, Note (9) Min Typ Max Min Typ Max 100 10 300 150 20 500 Unit A mA Notes to tables: (1) (2) (3) (4) (5) (6) (7) See Operating Requirements for Altera Devices in the current Altera Data Book. Voltage with respect to ground; all over- and undershoots due to system or tester noise are included. Minimum DC input is -0.5 V. During transitions, the inputs may undershoot to -2.0 V or overshoot to 7.0 V for periods of less than 20 ns under no-load conditions. Under bias. Extended temperature versions are also available. Operating conditions: V CC = 5 V 5%, TA = 0 C to 70 C for commercial use. V CC = 5 V 10%, TA = -40 C to 80 C for industrial use. Test one output at a time; test duration should not exceed one second. For EP312 devices: DIP packages, VPP is on pin 1 PLCC packages, VPP is on pin 2 For EP324 devices: DIP packages, VPP is on pin 18 PLCC packages, VPP is on pin 20 When the Turbo Bit is not set (non-turbo mode), an EP312 or EP324 device enters standby mode if no logic transitions occur for 100 ns after the last transition. For EP312 devices: parameter measured with device configured as one 12-bit counter. For EP324 devices: parameter measured with device configured as two 12-bit counters. t4U.com (8) (9) DataShee .com .com 12 Altera Corporation DataSheet 4 U .com www..com EP312 & EP324 Classic EPLDs AC Operating Conditions: EP312 Combinatorial Mode Symbol tPD1 tPD2 tPZX tPXZ tPCLR tPSET Note (1) EP312-25 EP312-30 Non-Turbo Adder Parameter Input to non-registered output I/O to non-registered output Input or I/O to output enable, Note (3) Input or I/O to output disable, Note (3) Input or I/O to asynchronous reset Input or I/O to asynchronous set Conditions C1 = 35 pF C1 = 35 pF C1 = 35 pF C1 = 5 pF C1 = 35 pF C1 = 35 pF Min Max 25 25 25 25 25 25 Min Max 30 30 30 30 30 30 Note (2) 20 20 20 20 20 20 Units ns ns ns ns ns ns Synchronous Clock Mode (Macrocells) Symbol fMAX fCNT1 fCNT2 tSU1 EP312-25 EP312-30 Non-Turbo Adder Parameter Maximum frequency (pipelined), no feedback Maximum counter frequency, external feedback Maximum counter frequency, internal feedback Input or I/O setup time to global clock Input or I/O setup time to global clock Input or I/O hold time from global clock Global clock to output delay Minimum global clock period Clock low time Clock high time Clock period Min 66 33.3 33.3 15 15 0 Max Min 50 26.3 28.5 20 20 0 Max Note (2) Units MHz MHz MHz 20 20 0 18 35 0 20 0 0 0 ns ns ns ns ns ns ns t4U.comtSU1 tH tCO tCNT tCL tCH tCP ns DataShee .com 7 7 15 15 30 9 9 20 Synchronous Clock (Input Structure) Symbol fMAXI tSUIR tESUI tCOI tEOI tHI tEHI tCHI tCLI tCPI EP312-25 EP312-30 Non-Turbo Adder Parameter Maximum frequency input structure Input register/latch setup time to ILE/ICLK Input latch setup time to ILE, Note (4) ICLK to combinatorial output ILE up to combinatorial output Input hold after falling edge of ILE/ICLK Input hold after falling edge of ILE ILE/ICLK high time ILE/ICLK low time Minimum ICLK period Min 66 5 5 Max Min 50 5 5 Max Note (2) 0 0 Units MHz ns ns ns ns ns ns ns ns ns 35 35 7 7 7 7 15 10 10 9 9 20 40 40 20 20 0 0 0 0 0 .com Altera Corporation 13 DataSheet 4 U .com www..com EP312 & EP324 Classic EPLDs Asynchronous Clock Mode (Macrocells) Symbol fAMAX fACNT1 fACNT2 tASU1 tASU1 tAH tACO tACNT tACL tACH tACP EP312-25 EP312-30 Non-Turbo Adder Parameter Maximum frequency (pipelined), no feedback Maximum counter frequency, external feedback Maximum counter frequency, internal feedback Input or I/O setup time to asynchronous clock Input or I/O setup time to asynchronous clock Input or I/O hold time from asynchronous clock Asynchronous clock to output delay Minimum global clock period Asynchronous clock low time Asynchronous clock high time Minimum asynchronous clock period Min 66 28.5 33.3 10 10 5 Max Min 50 23.8 30 12 12 5 Max Note (2) Units MHz MHz MHz 20 20 0 30 35 20 20 20 20 20 ns ns ns ns ns ns ns ns 25 30 7 7 15 9 9 20 Asynchronous Clock (Input Structure) Symbol f t4U.comAMAXI tASUIR tAESUI tACOI tAEOI tAHI tAEHI tACHI tACLI tACPI EP312-25 EP312-30 Non-Turbo Adder Parameter Maximum frequency input structure Input register/latch setup time to asynchronous ILE/ICLK Asynchronous ICLK to combinatorial output Asynchronous ILE up to combinatorial output Input hold after falling edge of asynchronous ILE/ICLK Input hold after falling edge of asynchronous ILE Asynchronous ILE/ICLK high time Asynchronous ILE/ICLK low time Minimum ICLK period Min 66 0 Max Min 50 0 0 Max Note (2) 0 0 Units ns ns ns ns ns ns ns ns ns MHz DataShee Input latch setup time to asynchronous ILE, Note (4) 0 .com 48 48 20 20 7 7 15 55 55 25 25 9 9 20 20 20 20 0 20 20 20 Input Clock to Macrocell Clock Symbol tC1C2 tC1C2 tC1C2 tC1C2 EP312-25 EP312-30 Non-Turbo Adder Parameter Synchronous ILE/ICLK to synchronous macrocell CLK Synchronous ILE/ICLK to asynchronous macrocell CLK Asynchronous ILE/ICLK to synchronous macrocell CLK Asynchronous ILE/ICLK to asynchronous macrocell CLK Min Max 25 15 35 25 Min Max 30 18 40 35 Note (2) 20 20 20 20 Units ns ns ns ns Operating conditions: V CC = 5 V 5%, T A = 0 C to 70 C for commercial use. V CC = 5 V 10%, T A = -40 C to 85 C for industrial use. (2) If the device is operating in standby mode, increase the time by the amount shown. (3) The tPZX and tPXZ parameters are measured at 0.5 V from steady-state voltage that is driven by the specified output load. (4) This specification must be met to guarantee tEOI. If ILE goes high before data is valid, use tPD instead of tEOI. .com (1) Notes to tables: 14 Altera Corporation DataSheet 4 U .com www..com EP312 & EP324 Classic EPLDs AC Operating Conditions: EP324 Combinatorial Mode Symbol tPD1 tPD2 tPZX tPXZ tPCLR tPSET Note (1) EP324-25 EP324-30 Non-Turbo Adder Parameter Input to non-registered output I/O to non-registered output, Input or I/O to output enable, Note (3) Input or I/O to output disable, Note (3) Input or I/O to asynchronous reset Input or I/O to asynchronous set Conditions Min C1 = 35 pF C1 = 35 pF C1 = 35 pF C1 = 5 pF C1 = 35 pF C1 = 35 pF Max 25 25 25 25 25 25 Min Max 30 30 30 30 30 30 Note (2) 20 20 20 20 20 20 Units ns ns ns ns ns ns Synchronous Clock Mode (Macrocells) Symbol fMAX fCNT1 fCNT2 tSU1 tSU1 tCO tCNT tCL tCH tCP EP324-25 EP324-30 Non-Turbo Adder Parameter Maximum frequency (pipelined), no feedback Maximum counter frequency, external feedback Maximum counter frequency, internal feedback Input or I/O setup time to global clock Input or I/O setup time to global clock Input or I/O hold time from global clock Global clock to output delay Minimum global clock period Clock low time Clock high time Clock period Min 66 33.3 33.3 12.5 12 0 Max Min 50 25 28.5 20 20 0 Max Note (2) Units MHz MHz MHz 20 20 0 20 35 0 20 0 0 0 ns ns ns ns ns ns ns ns t4U.comtH DataShee 17.8 .com 7 7 15 30 9 9 20 Synchronous Clock Mode (Input Structure) Symbol fMAXI tSUIR tESUI tCOI tEOI tHI tEHI tCHI tCLI tCPI EP324-25 EP324-30 Non-Turbo Adder Parameter Maximum frequency input structure Input register/latch setup time to ILE/ICLK Input latch setup time to ILE, Note (4) ICLK to combinatorial output ILE up to combinatorial output Input hold after falling edge of ILE/ICLK Input hold after falling edge of ILE ILE/ICLK high time ILE/ICLK low time Minimum ICLK period Min 66 1 1 Max Min 50 2.5 2.5 Max Note (2) 0 0 Units MHz ns ns ns ns ns ns ns ns ns 30 30 8 7 7 7 15 9 8 9 9 20 35 35 20 20 0 0 0 0 0 .com Altera Corporation 15 DataSheet 4 U .com www..com EP312 & EP324 Classic EPLDs Asynchronous Clock Mode (Macrocells) Symbol fAMAX fACNT1 fACNT2 tASU1 tASU1 tAH tACO tACNT tACL tACH tACP EP324-25 EP324-30 Non-Turbo Adder Parameter Maximum frequency (pipelined), no feedback Maximum counter frequency, external feedback Maximum counter frequency, internal feedback Input or I/O setup time to asynchronous clock Input or I/O setup time to asynchronous clock Input or I/O hold time from asynchronous clock Asynchronous clock to output delay Minimum global clock period Asynchronous clock low time Asynchronous clock high time Minimum asynchronous clock period Min Max 66 27.7 33.3 11 11 3 25 30 7 7 15 Min Max 50 23.8 28.5 12 12 4 30 35 9 9 20 Note (2) Units MHz MHz MHz 20 20 0 20 20 20 20 20 ns ns ns ns ns ns ns ns Asynchronous Clock Mode (Input Structure) Symbol f t4U.comAMAXI tASUIR tAESUI tACOI tAEOI tAHI tAEHI tACHI tACLI tACPI EP324-25 EP324-30 Non-Turbo Adder Parameter Maximum frequency input structure Input register/latch setup time to asynchronous ILE/ICLK Asynchronous ICLK to combinatorial output Asynchronous ILE up to combinatorial output Input hold after falling edge of asynchronous ILE/ICLK Input hold after falling edge of asynchronous ILE Asynchronous ILE/ICLK high time Asynchronous ILE/ICLK low time Minimum ICLK period Min Max 66 -5 30 30 15 14 7 7 15 Min Max 50 -5 -5 35 45 18 17 9 9 20 Note (2) 0 0 20 20 20 0 20 20 20 Units MHz ns ns ns ns ns ns ns ns ns DataShee Input latch setup time to asynchronous ILE, Note (4) -5 .com Input Clock to Macrocell Clock Symbol tC1C2 tC1C2 tC1C2 tC1C2 EP324-25 EP324-30 Non-Turbo Adder Parameter Synchronous ILE/ICLK to synchronous macrocell CLK Synchronous ILE/ICLK to asynchronous macrocell CLK Asynchronous ILE/ICLK to synchronous macrocell CLK Asynchronous ILE/ICLK to asynchronous macrocell CLK Min Max 20 12.5 40 20 Min Max 25 15 45 25 Note (2) 20 20 20 20 Units ns ns ns ns Notes to tables: (1) (2) (3) (4) .com 16 Operating conditions: V CC = 5 V 5%, T A = 0 C to 70 C for commercial use. If the device is operating in standby mode, increase the time by the amount shown. The tPZX and tPXZ parameters are measured at 0.5 V from steady-state voltage that is driven by the specified output load. This specification must be met to guarantee tEOI. If ILE goes high before the data is valid, use tPD instead of tEOI. Altera Corporation DataSheet 4 U .com www..com EP312 & EP324 Classic EPLDs Figure 8 shows the package pin-outs for EP312 and EP324 devices. Figure 8. EP312 & EP324 Package Pin-Outs Package outlines not drawn to scale. Windows in ceramic packages only. CLK/INPUT INPUT VCC VCC I/O I/O 27 CLK/INPUT I/O INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT I/O GND 1 2 3 4 5 6 7 8 9 24 23 22 21 20 19 18 17 16 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O 4 INPUT INPUT INPUT INPUT INPUT INPUT NC 5 6 7 8 9 10 11 12 INPUT 3 2 1 28 26 25 24 23 22 21 I/O I/O I/O I/O I/O I/O I/O NC EP312 13 I/O 14 GND 15 GND 16 ILE/ICLK/INPUT 17 I/O 20 19 18 I/O EP312 10 11 12 15 14 13 I/O ILE/ICLK/INPUT t4U.com 24-Pin DIP .com DataShee 28-Pin J-Lead CLK/INPUT INPUT INPUT INPUT INPUT INPUT NC I/O I/O I/O CLK/INPUT INPUT INPUT I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O INPUT INPUT INPUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 INPUT INPUT INPUT I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O INPUT INPUT ILE/ICLK/INPUT I/O I/O GND I/O I/O NC I/O I/O VCC I/O I/O 7 8 9 10 11 12 13 14 15 16 17 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 I/O I/O VCC I/O I/O NC I/O I/O GND I/O I/O EP324 18 19 20 21 22 23 24 25 26 27 28 I/O ILE/ICLK/INPUT INPUT INPUT INPUT INPUT INPUT I/O I/O NC I/O I/O 29 EP324 16 17 18 19 20 25 24 23 22 21 40-Pin DIP 44-Pin J-Lead .com Altera Corporation 17 DataSheet 4 U .com www..com EP312 & EP324 Classic EPLDs Package Outlines Product Availability Refer to "Altera Device Package Outlines" in the Altera Data Book for detailed information on packages outlines. Table 3 gives the availability and ordering codes for EP312 and EP324 devices. Altera will accept Intel product names and ordering codes for Intel devices until June 30, 1995, after which only Altera product names and ordering codes will be accepted. Table 3. EP312 & EP324 Availability Device EP312 Temperature Grade Commercial temperature (0 C to 70 C) Speed Grade -25 -30 -25 -30 -25 -30 Package 24-pin CerDIP 24-pin CerDIP 24-pin PDIP 24-pin PDIP 28-pin PLCC 28-pin PLCC Altera Ordering Code EP312DC-25 EP312DC-30 EP312PC-25 EP312PC-30 EP312LC-25 EP312LI-30 Former Intel Ordering Code D5AC312-25 D5AC312-30 P5AC312-25 P5AC312-30 N5AC312-25 TNAC312-30 t4U.com EP324 Industrial temperature (-40 C to 85 C) Commercial temperature (0 C to 70 C) -30 -25 -30 -25 -30 40-pin CerDIP EP324DC-30 .com 40-pin PDIP EP324PC-25 40-pin PDIP EP324PC-30 44-pin PLCC EP324LC-25 44-pin PLCC EP324LC-30 D5AC324-30 P5AC324-25 P5AC324-30 N5AC324-25 N5AC324-30 (R) .com 18 2610 Orchard Parkway San Jose, CA 95134-2020 (408) 894-7000 Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 894-7104 Literature Services: (408) 894-7144 Altera, MAX, MAX+PLUS, and FLEX are registered trademarks of Altera Corporation. The following are trademarks of Altera Corporation: MAX+PLUS II, AHDL, and FLEX 10K. Altera acknowledges the trademarks of other organizations for their respective products or services mentioned in this document, specifically: Verilog and Verilog-XL are registered trademarks of Cadence Design Systems, Inc. Mentor Graphics is a registered trademark of Mentor Graphics Corporation. Synopsys is a registered trademark of Synopsys, Inc. Viewlogic is a registered trademark of Viewlogic Systems, Inc. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Copyright (c) 1996 Altera Corporation. All rights reserved. Altera Corporation Printed on Recycled Paper. DataSheet 4 U .com |
Price & Availability of EP312
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